6. PBIT(Powerup Built In Test) Details and Demonstration

6.1 Description

(a) PBIT is completed appropriately 2~3 seconds after powerup. PBIT is performed only once, and its result is retained. The PBIT result is returned only when a PBIT_REQUEST is received, and there is no limit on the number of requests.

(b) [PBIT] During the powerup phase of ServoMax, if an error occurs, ServoMax does not initiate motor control and remains in the idle state.

(c) [CBIT] During operation (CBIT), ServoMax continuously monitors abnormal conditions. Even if a CBIT error occurs, motor control continues and does not stop. This is because stopping the motor to protect ServoMax could cause greater damage to the user’s system.

6.2 PBIT Demonstration

(a) Operational data(real-time monitoring) and PBIT information response share the same OP RESP Msg0/1.

(b) This section provides demonstration results for two cases via PBIT Request; when a PBIT error is present and when no PBIT error is present.

(c) Since this demonstration uses a DBC File, the CAN Signal values in the Output Window are decoded based only on the bits assigned to each signal. For example, although OP CMD Msg Byte[1] containing PBIT_NORMAL_REQ(_ECHO) is 0xA0(PBIT_REQ), only the upper 3 bits are decoded as C_PBIT_REQUEST_5 = 5.

6.2.1 PBIT Error, Request and Return

Figure 10. OP CMD Msg, PBIT Request

Figure 11. OP RESP Msg0/1, PBIT Return with PBIT Error Data

6.2.2 PBIT Normal, Return

The PBIT Request is used with the OP CMD Msg in the previous section, and the return is as follows.

Figure 12. OP RESP Msg0/1, PBIT Return with PBIT all Normal Data

6.3 BIT Error Allocation and Corrective Actions

(a) The table below explains the meaning of the 8-byte PBIT matrix. As the name implies, PBIT errors are generally not easily resolved by the user and may require troubleshooting by the manufacturer.

(b) The orange-colored errors below, while still limited in scope, are errors for which the user may attempt corrective actions. For all other errors, please contact the manufacturer. (Additionally, some of these errors are classified as CBIT and are also provided in real time via OP RESP Msg0.)

(c) Byte0.Bit0(under PBIT Master) is not a separate error, but rather a representative flag. It is set if any single error is present during the PBIT phase.

Table 7. PBIT Matrix and error coverage allocation

Table 8. PBIT/CBIT Details and Corrective Actions

6.4 Product BIT threshold

Table 9. Product BIT engagement threshold